1. Field of the Invention
This invention relates to a layout method for a semiconductor device, and more particularly to a layout method of a clock tree for shortening the design period of a semiconductor integrated circuit.
2. Description of the Related Art
In recent years, with development of semiconductor technology, large-scaling, complication and high integration of the semiconductor integrated circuit have been advanced. Particularly, in a system LSI in which a large number of soft cores and hard cores are used, the clock system is complicated so that the number of designing man-hours for creating a clock tree in a layout step for the design of semiconductor integrated circuits is increased. This greatly influences a designing schedule.
In the design of the clock tree in recent years, it is an important theme to solve not only reduction of clock skew but also the problems of power consumption, transistor deterioration due to miniaturization, delay error due to process change, etc.
In the design of the clock tree, in order to reduce the changing error in transistors to be used, the number of steps of the clock tree and cell type are made equivalent to implement equivalent-length wirings and equivalent loads. This cannot be implemented easily only by a conventional skew adjusting technique. Thus, the creation of the clock tree entailed considerable labor.
Further, in the layout design of the semiconductor integrated circuit which has been large-scaled and complicated, in many cases, a circuit modification or change is carried out. In order to implement the layout in a short time after a final RTL specification has been determined, generally, provisional layout is implemented before the RTL specification is determined, thereby creating the clock tree.
However, even if the clock tree with low power consumption and tough to changes and crosstalk is designed by consuming considerable labor for the provisional layout and further saved, there has not been proposed an efficient means for reproducing the clock tree having the same technical idea for the circuit re-recomposed after the circuit modification occurs. Therefore where the modification has been made for the RTL, the design of the clock tree must be restructured from the beginning. Thus, the period taken for designing the clock tree in a final layout step becomes equal to the designing period taken for during the provisional layout.
As a countermeasure for such a problem, conventionally, there has been developed a technique for making the design effective by facilitating the skew adjustment by “hardmarco” organization of the clock tree (for example, see Japanese Patent No. 3112843). FIG. 6 is a flowchart showing the process for designing the clock tree according to a prior art.
In FIG. 6, in step 601, circuit design is made. In step 602, the clock inserted in the circuit is “hardmacro” organized. In step 603, forward annotation is performed. If the result is OK, the processing proceeds to the subsequent step 604. If the result is NG, the designing process returns to the circuit design of step 601.
In step 604, blocks of the “hardmacro” in step 603 and step 602 are arranged. In step 605, wiring of automated arrangement is made. In step 606, back annotation is performed. If the result is OK, the designing process is ended. If the result is NG, the designing process returns to the circuit design in step 601 again. By such a clock tree creating method, the skew adjustment is facilitated.
The prior art described above is a technique for minimizing the clock skew. However, if the timing of the circuit cannot be made satisfactory in the back annotation after the arrangement wiring has been made, the process for designing the clock tree must be returned to the circuit designing. Thus, the prior art is not an efficient means for shortening the period from the determination of the final RTL specification to the end of the layout, and so is problematic in the efficiency of design.
Further, in the prior art, since the wiring of the automated arrangement is made after the “hardmacro” has been arranged, the connection between the flip-flops and hardmacro arranged generates wiring disorder so that the clock skew may be deteriorated. Even where the flip-flops to be connected to the “hardmacro” are arranged adjacently to the hardmacro taking the wiring disorder of the clock into consideration, the timing of data path may be deteriorated.